1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory such as a mask ROM.
2. Description of the Background Art
In general, a mask ROM is known as an exemplary memory, as disclosed in Japanese Patent Laying-Open No. 5-275656 (1993), for example.
FIG. 34 is a plane layout diagram showing the structure of a conventional contact-type mask ROM. FIG. 35 is a sectional view of the conventional contact-type mask ROM taken along the line 500-500 in FIG. 34. Referring to FIGS. 34 and 35, a plurality of impurity regions 202 containing an impurity diffused therein are formed on the upper surface of a substrate 201 at prescribed intervals in the conventional contact-type mask ROM. A word line 204 functioning as a gate electrode is formed on an upper surface portion of the substrate 201 corresponding to a clearance between each adjacent pair of impurity regions 202 through a gate insulating film 203. This word line 204, the gate insulating film 203 and the corresponding pair of impurity regions 202 form each transistor 205. A first interlayer dielectric film 206 is formed to cover the upper surface of the substrate 201 and the word lines 204. The first interlayer dielectric film 206 has contact holes 207 formed in correspondence to the respective impurity regions 202, and first plugs 208 are embedded in the contact holes 207 to be connected to the impurity regions 202 respectively.
Source lines (GND lines) 209 and connection layers 210 are provided on the first interlayer dielectric film 206, to be connected to the first plugs 208. Each transistor 205 is provided every memory cell 211. A second interlayer dielectric film 212 is formed on the first interlayer dielectric film 206 to cover the source lines (GND lines) 209 and the connection layers 210. Contact holes 213 are formed in regions of the second interlayer dielectric film 212 located on prescribed ones of the connection layers 210, while second plugs 214 are embedded in the contact holes 213. Bit lines 215 are formed on the second interlayer dielectric film 212, to be connected to the second plugs 214. Thus, the bit lines 215 are connected with the impurity regions 202 of the transistors 205.
In the conventional contact-type mask ROM, those of the transistors 205 provided with the second plugs 214 are connected (contacted) to the corresponding bit lines 215. Each memory cell 211 stores data “0” or “1” in response to whether or not the transistor 205 included therein is connected to the corresponding bit line 215.
In the conventional mask ROM shown in FIG. 34, however, the memory cell size is disadvantageously increased due to the transistors 205 provided in correspondence to the respective memory cells 211.